FET and bipolar junction transistor (BJT) are well-known electronic devices and have been used for various applications. Even though FET is similar to BJT in its characteristics and functions, it is much simpler and better for use than BJT, because of the non-zero base current and low input impedance inherently possessed by BJT which will result in disadvantages when it is used for circuit applications. There are two typical FETs, i.e., metal-oxide-semiconductor (MOS) FET and JFET. Unfortunately, the well-developed circuits for driving MOSFETs are not applicable for driving JFETs for their different gate driving mechanisms. Therefore, modification is proposed for example by Lovoltech in which parallel resistor and capacitor network is introduced into the driver circuit prior to the gate of the driven JFET in addition to PWM control circuit, see http://www.lovoltech.com/pdf/an100.pdf and http://www.lovoltech.com/pdf/AN 101-112003.pdf.
For more detail, the art proposed by Lovoltech is shown in FIG. 1, in which a parallel resistor and capacitor network 10 for driving an N-channel depletion-type JFET 12 comprises a capacitor 102 connected between a control input 106 and the gate G of the JFET 12, and a resistor 104 connected to the capacitor 102 in parallel. Voltage VI is applied to the circuit 10 on the control input 106, and thus, the voltage difference between the control input 106 of the circuit 10 and the source of the JFET 12 isVIS=VI−VS,  EQ-1where VS is the voltage on the source of the JFET 12. In this illustration, the source of the JFET 12 is grounded, and it is therefore obtainedVIS=VI.  EQ-2Furthermore, according to Kirchhoff's voltage law, it is obvious thatVIS=VC+VGS,  EQ-3where VC is the voltage drop across the capacitor 102 and VGS is the gate-source voltage of the JFET 12. In combination of the equation EQ-2 with the equation EQ-3, it leads toVGS=VI−VC.  EQ-4When the voltage VI is at a high level, the gate-source voltage VGS of the JFET 12 is positive, since the charged voltage VC of the capacitor 102 cannot be higher than VI. As a result, the JFET 12 is conductive. When the voltage VI is switched to a level lower than VC, the gate-source voltage VGS of the JFET 12 becomes negative, resulting in cutoff of the JFET 12.
However, when such apparatus 10 turns on the N-channel depletion-type JFET 12, the gate of the JFET 12 is forward biased and therefore, a very high current is conductive between its gate and source, which makes it not suitable for low power applications such as portable apparatus.
Accordingly, it is desired a circuit for driving a depletion-type JFET without high gate-source current generated when the depletion-type JFET is turned on.